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Showing 10 out of a total of 48 results for collection: 2006 - Proceedings of 12th International Workshop on Thermal investigations of ICs. (0.025 seconds)
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(TIMA Editions , Grenoble, France, 2006)We will describe the thermal performance of power semiconductor module, which consists of hetero-junction bipolar transistors (HBTs), for mobile communication systems. We calculate the thermal resistance between the HBT fingers and the bottom surface of a multi-layer printed circuit board (PCB) using a finite element method (FEM). We applied a steady state analysis to evaluate the influence of design parameters on thermal resistance of the module. We found that the thickness of GaAs substrate, the thickness of multi-layer circuit board, the thermal conductivity of bonding material under GaAs substrate, and misalignment of thermal vias between each layer of PCB are the dominant parameter in thermal resistance of the module....
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(TIMA Editions , Grenoble, France, 2006)A nonlinear projection-base approach for generating compact models of nonlinear thermal networks is proposed. This approach is an extension of Galerkin's method, based on the theory of kernels. High accuracy for large temperature variations and high compactness of the generated models can be obtained....
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(TIMA Editions , Grenoble, France, 2006)Thermoreflectance methods by picosecond pulse heating and by nanosecond pulse heating have been developed under the same geometrical configuration as the laser flash method by the National Metrology Institute of JAPAN, AIST. Using these light pulse heating methods, thermal diffusivity of each layer of multilayered thin films and boundary thermal resistance between the layers can be determined from the observed transient temperature curves based on the response function method. The measurement results of various thin films as transparent conductive films used for flat panel displays, hard coating films and multilayered films of the next generation phase-change optical disk will be presented....
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(TIMA Editions , Grenoble, France, 2006)Manufacturing electronic devices by printing techniques with low temperature sintering of nano-size material particles can revolutionize the electronics industry in coming years. The impact of this change to the industry can be significant enabling low-cost products and flexibility in manufacturing. implementation of a new production technology with new materials requires thorough elementary knowledge creation. It should be noticed that although some of first electronic devices ideally can be manufactured by printing, at the present several modules are in fact manufactured by using hybrid techniques (for instance photolithography, vapor depositions, spraying, etc...)....
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(TIMA Editions , Grenoble, France, 2006)A new experimental tool for analyzing the topography and deformation of electronics components under thermo-mechanical stress is presented. Application examples are shown for a great variety of components, for localizing and quantifying deformations of electronic assemblies. Cooling and heating cycles following JEDEC type thermal profiles have been applied on different components, both before and after assembly. Simultaneously, real time topography and deformation measurements are obtained. These capabilities constitute a powerful tool for failure prediction, risk evaluation, and accelerated development. The high resolution optical setup allows analysis of deformations in the micrometer range, even for very irregularly shaped surfaces....
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(TIMA Editions , Grenoble, France, 2006)In the Square Kilometre Array (SKA) telescope [1], [2], the noise temperature of the first LNA must be reduced in order to reduce the necessary active area and the total system costs. Cooling the LNA locally would significantly decrease the noise figure but also the necessary power since not the whole system has to be cooled. For optimal thermal isolation, an LNA chip which only needs 6 bondwires has been chosen, 4 Ground and 2 signal wires. Biasing occurs on-chip. If the bondwires are 1.5mm long, the total heat conduction of the 6 bondwires is 31 mW, which is added to the power consumption of the LNA (30 mW). With a power of 61 mW to cool, the Peltier element can achieve a -T of 60K. With this system, a noise reduction of 30% has been measured with 0.5W of electrical power. For 15% noise reduction, only 35mW of electrical power was needed....
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(TIMA Editions , Grenoble, France, 2006)Thermal measurement and modeling of multi-die packages became a hot topic recently in different fields like RAM chip packaging or LEDs / LED assemblies, resulting in vertical (stacked) and lateral arrangement. In our present study we show results for a mixed arrangement : an opto-coupler device has been investigated with 4 chips in lateral as well as vertical arrangement. In this paper we give an overview of measurement and modeling techniques and results for stacked and MCM structures, describe our present measurement results together with our structure function based methodology of validating the detailed model of the package being studied. Also, we show how to derive junction-to-pin thermal resistances with a technique using structure functions....
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(TIMA Editions , Grenoble, France, 2006)As device dimensions shrink into the nanometer range, power and performance constraints prohibit the longevity of traditional MOS devices in circuit design. A finFET, a quasi-planar double-gated device, has emerged as a replacement. FinFETs are formed by creating a silicon em fin which protrudes out of the wafer, wrapping a gate around the fin, and then doping the ends of the fin to form the source and drain. Wider finFETs are formed using multiple fins between the source and drain regions. While finFETs provide promising electrostatic characteristics, they, like other ultra-thin body nano devices, have the potential to suffer from significant self heating. We study in this paper self heating in multi-fin devices. We first propose a distributed thermal channel model and validate it using ANSYS. We use this model to study the electro-thermal properties of multi-fin devices with both flared and rectangular channel extensions. We analyze variations in fin geometric parameters such as fin width, gate length, and fin and gate height, and we investigate the impact on thermal sensitivity. We utilize a thermal sensitivity metric, METS, to characterize device thermal robustness. We provide experimental data to validate our findings. Our work is novel as it is the first to address thermal issues within multi-fin devices. Furthermore, it provides an impetus for further research on the emerging area of electro-thermal device and circuit design....
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(TIMA Editions , Grenoble, France, 2006)This communication deals with a theoretical study of the hot spot onset (HSO) in cellular bipolar power transistors. This well-known phenomenon consists of a current crowding within few cells occurring for high power conditions, which significantly decreases the forward safe operating area (FSOA) of the device. The study was performed on a virtual sample by means of a fast, fully analytical electro-thermal simulator operating in the steady state regime and under the condition of imposed input base current. The purpose was to study the dependence of the phenomenon on several thermal and geometrical factors and to test suitable countermeasures able to impinge this phenomenon at higher biases or to completely eliminate it. The power threshold of HSO and its localization within the silicon die were observed as a function of the electrical bias conditions as for instance the collector voltage, the equivalent thermal resistance of the assembling structure underlying the silicon die, the value of the ballasting resistances purposely added in the emitter metal interconnections and the thickness of the copper heat spreader placed on the die top just to the aim of making more uniform the temperature of the silicon surface....
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(TIMA Editions , Grenoble, France, 2006)Power consumption and heat dissipation become key elements in the field of high-end integrated circuits, especially those used in mobile and high-speed applications, due to their increase of transistor count and clock frequencies. Dynamic thermal management strategies have been proposed and implemented in order to mitigate heat dissipation. However, there is a lack of a tool that can be used to evaluate DTM strategies and thermal response of real life systems. Therefore, in this paper we introduce and define the concepts of thermal benchmark software and power benchmark software as a software application for run-time system level thermal and power characterization...