A Low-cost Through Via Interconnection for ISM WLP

Abstract

WLP (Wafer level packaging) for image sensor devices has the advantage of small size, high performance and low cost, and becomes more and more important for ISM (image sensor module) products. In the WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed such as T-contact and TSV (Through Silicon Via). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Basic vertical via shape and low cost interconnection processes are adopted, compared to tapered via interconnection processes. Via etch problem caused by CIS wafer thickness non-uniformity was solved by remaining a fillet structure at the bottom of vias. This structure can prevent via notch and give better result of seed layer deposition and via filling.