Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

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URI: http://hdl.handle.net/2042/14688
Title: Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm
Author: Szczesniak, W.
Abstract: VLSI CMOS digital circuits, average temperature reduction, balancing power dissipation, system reliability, scheduling algorithmThis paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.
Subject: VLSI CMOS digital circuits, average temperature reduction, balancing power dissipation, system reliability, scheduling algorithm
Publisher: EDA Publishing Association, Grenoble, France
Date: 2007

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